This invention relates to integrated circuit devices, and more particularly to 10 Gigabit Ethernet (10 GbE) physical (PHY) layer circuitry for use in programmable integrated circuit devices.
As the demand for network bandwidth increases, the adoption of 10 GbE is gaining a great deal of momentum for use in local area networks (LANs), wide area networks (WANs), and metropolitan area networks (MANs). 10 GbE is a version of Ethernet with a nominal data rate of 10 Gigabits per second and is specified by the IEEE 802.3ae standard. The IEEE 802.3ae standard is incorporated by reference herein in its entirety. Due to the high speed and demanding specifications of the 10 GbE standard, especially at the PHY layer, performance is a key differentiating factor between network equipment providers.
The PHY layer of 10 GbE can be implemented by integrating a number of available components that communicate via standard interfaces. For example, a typical 10 GbE PHY layer may be implemented by connecting a network processor to a 10 GbE Media Access Control (MAC) device via a 16-bit double data rate (DDR) System Physical Interface Level 4 (SPI-4) interface standard. The network processor and MAC devices are technically not part of the PHY layer, but are included in the description of the PHY layer to give context to the manner in which the PHY layer connects to higher network layers. The MAC device may be connected to a Physical Coding Sublayer (PCS) device via 64-bit 10 Gigabit Media Independent Interface (XGMII). XGMII is a standard for connecting full duplex 10 GbE ports to each other and to other electronic devices on a printed circuit board. The PCS device is connected to a 10 GbE optical transceiver via 10 Gigabit Ethernet 16-bit Interface (XSBI). Finally, the optical transceiver transmits and receives a 10 GbE optical signal. Even though this 10 GbE PHY layer implementation can be designed using available components, integrating such a PHY layer design within a system requires many components, uses a large amount of circuit board area, and creates potentially complex layout and interoperability issues.
It is therefore desirable to give integrated circuit devices and especially programmable integrated circuit devices such as programmable microcontrollers, programmable logic devices (“PLDs”), etc., the ability implement 10 GbE solutions in a less complex and more efficient manner. The integration of PLDs with 10 GbE implementations generally involves generating higher level network devices (e.g., network controllers and MAC devices) within the PLD and connecting the PLD outputs to specially designed optical modules that implement the specialized 10 GbE PHY layer circuitry. However, these implementations do little to reduce the complexity of the 10 GbE implementations. The large bus protocols that are needed to connect the optical modules to the PLDs are complex and lead to reduced performance. Typically implementing these protocols within a PLD requires additional buffers, clock dividers, and reference clock signals which adds latency, timing constraints, and power consumption to the system. Further, compared to ordinary optical transceivers, the optical modules that must be used in this implementation are expensive and have high power and space requirements. Therefore it would be desirable to provide programmable integrated circuit devices that can implement the physical layer of 10 GbE circuitry.